Description of the Prior Art
In FIG. 1 of the drawings is shown in model form the cross sectional configuration of a semiconductor device structure 10 fabricated by a known semiconductor device process. The device structure 10 includes a semiconductor wafer 12 having a plurality of independent device-forming areas which are commonly represented by 14. On top of these device-forming areas 14 are provided interconnection wiring areas 16 which overlie the device-forming areas 14, respectively. The interconnection wiring areas 16 are arranged to be in contact with the individual device-forming areas 14. The wiring areas 16 in turn are respectively overlain by input/output terminal wiring areas 18 which selectively provide electrical connections to and from the individual interconnection wiring areas 16. Those of the device-forming areas 14, interconnection wiring areas 16 and input/output terminal wiring areas 18 which are shown vertically aligned together are assumed to form individual integrated circuit units or semiconductor chips.
FIGS. 2A and 2B of the drawings show the cross sectional configurations, at different stages of device fabrication process, of one of such integrated circuit units. At the beginning of the process stage illustrated in FIG. 2A, the semiconductor integrated circuit unit includes a semiconductor substrate 12' which forms part of the wafer 12 in the semiconductor device structure 10 shown in FIG. 1. On this semiconductor substrate 12' is provided a device-forming area including, by way of example, a plurality of bipolar transistor devices 14a and 14b and a plurality of resistor devices 14c and 14d. The transistor devices 14a and 14b and resistor devices 14c and 14d are isolated from one another by isolation regions 20 and are jointly covered with an interlevel insulator layer 22 which has a plurality of via holes 24 extending to the surfaces of the transistor and resistor devices 14a, 14b, 14c and 14d. These transistor devices 14a and 14b and resistor devices 14c and 14d form part of the device-forming areas 14 in the semiconductor device structure 10 shown in FIG. 1.
Turning to FIG. 2B, there are provided a plurality of interconnection wiring patterns 16' of metal which connect the transistor devices 14a and 14b and resistor devices 14c and 14d through the via holes 24 each other. The interconnection wiring patterns 16' for the transistor and resistor devices 14a, 14b, 14c and 14d as well as those portions of the interlevel insulator layer 22 as herein shown form one of the interconnection wiring areas 16 of the semiconductor device structure 10 illustrated in FIG. 1. The interconnection wiring patterns 16' and these portions of the interlevel insulator layer 22 are covered with a toplevel insulator layer 26 which has a plurality of via holes 28 extending to the surface of the interconnection wiring pattern 16'. On the interconnection wiring area is provided a plurality of input/output terminal wiring pstterns 18' of metal which overlie portions of the toplevel insulator layer 26 and which are selectively connected to the interconnection wiring patterns 16' through the via holes 28 in the insulator layer 26. The input/output terminal wiring patterns 18' form each of the input/output terminal wiring areas 18 of the semiconductor device structure 10 shown in FIG. 1.
FIG. 3 shows the general configuration in plan of the semiconductor integrated circuit unit thus fabricated at the end of the process stage illustrated in FIG. 2B, wherein the semiconductor integrated circuit unit as a whole is denoted by 30 and is shown having a device-forming area 32. The device-forming area 32 is assumed to be defined by the device regions 14a, 14b, 14c and 14d depicted in FIG. 2B and is shown surrounded by an input/output terminal area 34 including a number of input/output terminal pads 36 which are typically arranged along the edges of the integrated circuit unit 10 as shown. The input/output terminal area 34 forms part of each of the input/output terminal wiring areas 18 of the semiconductor device structure 10 shown in FIG. 1 with the input/output terminal pads 36 respectively leading from the input/output terminal wiring patterns 20'. The input/output terminal wiring patterns 18' also lie at the surface of the device structure 10 but these wiring patterns 18' are not herein shown for simplicity of illustration.
Assume, now, that the semiconductor integrated circuit unit 30 as a whole is square-shaped in plan and has a length Lc for each side thereof and that the device-forming area 32 in the integrated circuit unit 10 is also square-shaped in plan and has a length Ld for each side thereof as shown in FIG. 3. The length Ld of the sides of the device-forming area 32 must be considerably less than the length Lc of the sides of the integrated circuit unit 30 in order to provide an allowance for forming the input/output terminal area 34 over which the input/output terminal pads 36 are to be arranged along each side of the circuit unit 30. Assuming further that the integrated circuit unit 30 under consideration is provided as a logic gate array, the number P of the pins, viz., the input/output terminal pads 36 to be provided for the integrated circuit unit 30 is, as well known in the art, given by the formula: EQU P=KG.sup.n,
where K is a constant approximating 0.2, G is the number of the logic functions incorporated in the array, viz., the gates provided in the integrated circuit unit 30, and n is a constant approximating 0.6. If the integrated circuit unit 30 has 1000 logic gates, by way of example, then the number P of the input/output terminal pads 36 to be provided for the circuit unit 30 should be about 127 from the above formula, which means that a total of about 160 input/output terminal pads 36 are required including the terminal pads for the power supply. This in turn means that the particular integrated circuit unit 30 should be sized to have 40 input/output terminal pads 36 along each of its sides. In order that these input/output terminal pads 36 be wire bonded to the substrate of the chip package at a subsequent stage of device fabrication process, the individual input/output terminal pads 36 to be provided along each side of the integrated circuit unit 30 must be arranged at a pitch (represented by Pt in FIG. 3) of about 300 microns. To realize such arrangement of the input/output terminal pads 36, the length Lc of each side of the semiconductor integrated circuit unit 30 must be approximately EQU 0.3 mm.times.39+1.0 mm=12.7 mm
in consideration of the additional length of about 1.0 mm required for providing an allowance for each of the corner portions at the opposite ends of each side.
On the other hand, it is well known that the length Ld of each side of the device-forming area 32 can be made less than 7 mm for a semiconductor integrated circuit unit having 1000 logic gates. This means that the share of the input/output terminal area 34 in the total area of the integrated circuit unit 30 is about 5.7 mm (=12.7-7) in length along each side and about 112 mm.sup.2 (=12.7.sup.2 -7.sup.2) in area. This in turn means that the input/output terminal area 34 accounts for about 230 percent of the device-forming area 32 which is equal to about 1/3.3 of the total area (=approx. 161 mm.sup.2) of the integrated circuit unit 30. The input/output terminal area 34 is thus larger than the device-forming area 32 and, indeed, only less than one-third of the total area of the integrated circuit unit 30 can be utilized for the device-forming area 32.
As the integration density is increased for logic gate arrays formed by semiconductor integrated circuit units, the share of the input/output terminal area in the total area of each integrated circuit unit increases progressively and requires substantial reduction in the number of the integrated circuit units 30 which can be provided in a single wafer. This results in reduction in the yield of the integrated circuits to be fabricated.